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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調(diào)節(jié)ESD保護

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認證產(chǎn)品(AEC-Q100/Q101)

74ALVT16543DGG

2.5 V/3.3 V ALVT 16-bit registered transceiver (3-state)

The 74ALVT16543 is a high-performance BiCMOS product designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility up to 5 V. The device can be used as two 8-bit transceivers or one 16-bit transceiver.

The 74ALVT16543 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (nEAB) input and the A-to-B Latch Enable (nLEAB) input are LOW, the A-to-B path is transparent.

A subsequent LOW-to-HIGH transition of the nLEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With nEAB and nOEAB both LOW, the 3-State B output buffers are active and display the data present at the outputs of the A latches.

Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • 16-bit universal bus interface
  • 5 V I/O Compatible
  • 3-State buffers
  • Output capability: +64 mA/-32 mA
  • TTL input and output switching levels
  • Input and output interface capability to systems at 5 V supply
  • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
  • Live insertion/extraction permitted
  • Power-up 3-State
  • Power-up reset
  • No bus current loading when output is tied to 5 V bus
  • Latch-up protection exceeds 500mA per JEDEC Std 17
  • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

Applications

參數(shù)類型

型號 Package name
74ALVT16543DGG TSSOP56

封裝

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74ALVT16543DGG 74ALVT16543DGG,112
(935209940112)
Obsolete ALVT16543 Standard Procedure Standard Procedure SOT364-1
TSSOP56
(SOT364-1)
SOT364-1 SSOP-TSSOP-VSO-WAVE
暫無信息
74ALVT16543DGG,118
(935209940118)
Obsolete ALVT16543 Standard Procedure Standard Procedure SOT364-1_118
74ALVT16543DGGS
(935209940512)
Obsolete ALVT16543 Standard Procedure Standard Procedure 暫無信息
74ALVT16543DGGY
(935209940518)
Obsolete ALVT16543 Standard Procedure Standard Procedure 暫無信息

環(huán)境信息

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學(xué)成分 RoHS RHF指示符
74ALVT16543DGG 74ALVT16543DGG,112 74ALVT16543DGG rohs rhf rhf
74ALVT16543DGG 74ALVT16543DGG,118 74ALVT16543DGG rohs rhf rhf
74ALVT16543DGG 74ALVT16543DGGS 74ALVT16543DGG rohs rhf rhf
74ALVT16543DGG 74ALVT16543DGGY 74ALVT16543DGG rohs rhf rhf
品質(zhì)及可靠性免責聲明

文檔 (7)

文件名稱 標題 類型 日期
74ALVT16543 2.5 V/3.3 V ALVT 16-bit registered transceiver (3-state) Data sheet 2004-09-13
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
alvt16543 alvt16543 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT364-1 plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body Package information 2022-06-23
alvt16 alvt16 Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要設(shè)計/技術(shù)支持,請告知我們并填寫 應(yīng)答表 我們會盡快回復(fù)您。

模型

文件名稱 標題 類型 日期
alvt16543 alvt16543 IBIS model IBIS model 2013-04-08
alvt16 alvt16 Spice model SPICE model 2013-05-07
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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