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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車(chē)應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74AUP1G32GX

Low-power 2-input OR-gate

The 74AUP1G32 is a single 2-input OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial power-down mode operation

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類(lèi)型

型號(hào) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AUP1G32GX 0.8?-?3.6 CMOS ± 1.9 7.9 70 1 ultra low -40~125 X2SON5

封裝

型號(hào) 可訂購(gòu)的器件編號(hào),(訂購(gòu)碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74AUP1G32GX 74AUP1G32GX,125
(935298362125)
Active pG SOT1226-3
X2SON5
(SOT1226-3)
SOT1226-3 SOT1226-3_125

環(huán)境信息

型號(hào) 可訂購(gòu)的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74AUP1G32GX 74AUP1G32GX,125 74AUP1G32GX rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (8)

文件名稱(chēng) 標(biāo)題 類(lèi)型 日期
74AUP1G32 Low-power 2-input OR-gate Data sheet 2024-09-20
SOT1226-3 3D model for products with SOT1226-3 package Design support 2021-01-28
aup1g32 74AUP1G32 IBIS model IBIS model 2014-12-14
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_document_leaflet_Logic_X2SON_packages_062018 X2SON ultra-small 4, 5, 6 & 8-pin leadless packages Leaflet 2018-06-05
SOT1226-3 plastic thermal enhanced extremely thin small outline package; no leads;5 terminals; body 0.8 x 0.8 x 0.32 mm Package information 2020-08-27
SOT1226-3_125 X2SON5; Reel pack for SMD, 7''; Q3/T4 product orientation Packing information 2020-05-08
74AUP1G32GX_Nexperia_Product_Reliability 74AUP1G32GX Nexperia Product Reliability Quality document 2024-06-16

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請(qǐng)告知我們并填寫(xiě) 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱(chēng) 標(biāo)題 類(lèi)型 日期
aup1g32 74AUP1G32 IBIS model IBIS model 2014-12-14
SOT1226-3 3D model for products with SOT1226-3 package Design support 2021-01-28

訂購(gòu)、定價(jià)與供貨

型號(hào) Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線(xiàn)購(gòu)買(mǎi)
74AUP1G32GX 74AUP1G32GX,125 935298362125 Active SOT1226-3_125 10,000 訂單產(chǎn)品

樣品

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如果您沒(méi)有 Nexperia 的直接賬戶(hù),我們的全球和地區(qū)分銷(xiāo)商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷(xiāo)商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購(gòu)部件

型號(hào) 可訂購(gòu)的器件編號(hào) 訂購(gòu)代碼(12NC) 封裝 從經(jīng)銷(xiāo)商處購(gòu)買(mǎi)
74AUP1G32GX 74AUP1G32GX,125 935298362125 SOT1226-3 訂單產(chǎn)品
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