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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74AUP1G332GW

Low-power 3-input OR-gate

The 74AUP1G332 is a single 3-input OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類型

型號(hào) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AUP1G332GW 0.8?-?3.6 CMOS ± 1.9 6.8 70 1 ultra low -40~125 TSSOP6

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號(hào) 可訂購的器件編號(hào),(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74AUP1G332GW 74AUP1G332GW,125
(935280751125)
Active aG SOT363-2
TSSOP6
(SOT363-2)
SOT363-2 SOT363-2_125

環(huán)境信息

型號(hào) 可訂購的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74AUP1G332GW 74AUP1G332GW,125 74AUP1G332GW rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (9)

文件名稱 標(biāo)題 類型 日期
74AUP1G332 Low-power 3-input OR-gate Data sheet 2023-07-18
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11052 Pin FMEA for AUP family Application note 2019-01-09
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02
aup1g332 aup1g332 IBIS model IBIS model 2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
SOT363-2 plastic thin shrink small outline package; 6 leads; body width 1.25 mm Package information 2022-11-21
SOT363-2_125 TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientation Packing information 2022-11-04
74AUP1G332GW_Nexperia_Product_Reliability 74AUP1G332GW Nexperia Product Reliability Quality document 2024-06-16

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請(qǐng)告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
aup1g332 aup1g332 IBIS model IBIS model 2014-12-21
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價(jià)與供貨

型號(hào) Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74AUP1G332GW 74AUP1G332GW,125 935280751125 Active SOT363-2_125 3,000 訂單產(chǎn)品

樣品

作為 Nexperia 的客戶,您可以通過我們的銷售機(jī)構(gòu)訂購樣品。

如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號(hào) 可訂購的器件編號(hào) 訂購代碼(12NC) 封裝 從經(jīng)銷商處購買
74AUP1G332GW 74AUP1G332GW,125 935280751125 SOT363-2 訂單產(chǎn)品
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