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Click here for more information74HC75DB
Quad bistable transparent latch
The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Alternatives
Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
Complementary Q and Q outputs
VCC and GND on the center pins
CMOS input levels
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
參數(shù)類型
| 型號(hào) | Package name |
|---|---|
| 74HC75DB | SSOP16 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC75DB | 74HC75DB,112 (935188770112) |
Obsolete | HC75 |
SSOP16 (SOT338-1) |
SOT338-1 |
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE |
暫無信息 |
| 74HC75DB,118 (935188770118) |
Obsolete | HC75 | 暫無信息 |
環(huán)境信息
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HC75DB | 74HC75DB,112 | 74HC75DB |
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| 74HC75DB | 74HC75DB,118 | 74HC75DB |
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文檔 (8)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74HC75 | Quad bistable transparent latch | Data sheet | 2024-01-17 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SSOP16_SOT338-1_mk | plastic, shrink small outline package; 16 leads; 0.65 mm pitch; 6.2 mm x 5.3 mm x 2 mm body | Marcom graphics | 2017-01-28 |
| SOT338-1 | plastic, shrink small outline package; 16 leads; 0.65 mm pitch; 6.2 mm x 5.3 mm x 2 mm body | Package information | 2022-06-20 |
| SSOP-TSSOP-VSO-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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模型
No documents available
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74HC75DB
Quad bistable transparent latch
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