可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74LVC1G175GW | 74LVC1G175GW,125 | 935274948125 | SOT363-2 | 訂單產(chǎn)品 |
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Click here for more information74LVC1G175GW
Single D-type flip-flop with reset; positive-edge trigger
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Overvoltage tolerant inputs to 5.5 V
±24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74LVC1G175GW | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 3.1 | 300 | low | -40~125 | TSSOP6 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC1G175GW | 74LVC1G175GW,125 (935274948125) |
Active | YT |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
Series
文檔 (8)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC1G175 | Single D-type flip-flop with reset; positive-edge trigger | Data sheet | 2023-08-15 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| lvc1g175 | 74LVC1G175 IBIS model | IBIS model | 2014-10-20 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
| SOT363-2_125 | TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientation | Packing information | 2022-11-04 |
| 74LVC1G175GW_Nexperia_Product_Reliability | 74LVC1G175GW Nexperia Product Reliability | Quality document | 2024-06-16 |
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVC1G175GW | 74LVC1G175GW,125 | 935274948125 | Active | SOT363-2_125 | 3,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC1G175GW
Single D-type flip-flop with reset; positive-edge trigger
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