可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74LVC2G240DP | 74LVC2G240DP,125 | 935272529125 | SOT505-2 | 訂單產(chǎn)品 |
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Click here for more information74LVC2G240DP
Dual inverting buffer/line driver; 3-state
The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pins nOE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G240 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74LVC2G240DP | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | TSSOP8 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G240DP | 74LVC2G240DP,125 (935272529125) |
Active | V240 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
Series
文檔 (10)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G240 | Dual inverting buffer/line driver; 3-state | Data sheet | 2024-04-30 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| lvc2g240 | 74LVC2G240 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
| SOT505-2_125 | TSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation | Packing information | 2020-04-21 |
| 74LVC2G240DP_Nexperia_Product_Reliability | 74LVC2G240DP Nexperia Product Reliability | Quality document | 2024-06-16 |
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVC2G240DP | 74LVC2G240DP,125 | 935272529125 | Active | SOT505-2_125 | 3,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC2G240DP
Dual inverting buffer/line driver; 3-state
從安世半導體購買
| SKU | 庫存* | MOQ | 單位價格 | 數(shù)量 |
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