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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調(diào)節(jié)ESD保護

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認證產(chǎn)品(AEC-Q100/Q101)

74LVT16373ADL

3.3 V 16-bit transparent D-type latch; 3-state

The 74LVT16373A is a 16?-?bit D?-?type transparent latch with 3?-?state outputs. The device can be used as two 8?-?bit transparent latches or a single 16?-?bit transparent latch. The device features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8?-?bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D?-?input changes. When nLE is LOW the latches store the information that was present at the inputs a set?-?up time preceding the HIGH?-?to?-?LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the nOE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull?-?up resistors to define unused inputs

此產(chǎn)品已停產(chǎn)

Features and benefits

  • 16-bit transparent latch

  • 3-state buffers

  • Wide supply voltage range from 2.7 V to 3.6 V

  • BiCMOS high speed and output drive

  • Output capability: +64 mA/–32 mA

  • Direct interface with TTL levels

  • Overvoltage tolerant inputs to 5.5 V

  • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

  • Live insertion/extraction permitted

  • Power-up reset

  • Power-up 3-state

  • No bus current loading when output is tied to 5 V bus

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

  • Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to 85 °C

參數(shù)類型

型號 Package name
74LVT16373ADL SSOP48

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVT16373ADL 74LVT16373ADL,118
(935183110118)
Withdrawn / End-of-life LVT16373A SOT370-1
SSOP48
(SOT370-1)
SOT370-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
SOT370-1_118
74LVT16373ADL,112
(935183110112)
Obsolete LVT16373A 暫無信息

環(huán)境信息

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學(xué)成分 RoHS RHF指示符
74LVT16373ADL 74LVT16373ADL,118 74LVT16373ADL rohs rhf rhf
74LVT16373ADL 74LVT16373ADL,112 74LVT16373ADL rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (7)

文件名稱 標題 類型 日期
74LVT16373A 3.3 V 16-bit transparent D-type latch; 3-state Data sheet 2024-07-08
lvt16373a lvt16373a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT370-1 plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
lvt16 lvt16 Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱 標題 類型 日期
lvt16373a lvt16373a IBIS model IBIS model 2013-04-09
lvt16 lvt16 Spice model SPICE model 2013-05-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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